Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language

Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizations fo r programmable systems assumed a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for the application. Howevel; such a processormemory eo-exploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem conjiguration, and pelform exploration of the memory architecture to trade-off cost versus performance. We present a set of experiments using our Memory-Aware Architectural Description Language to drive the exploration of the memory subsystem for the TIC621 I processor architecture, demonstrating a range of cost and pelformanee attributes.